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CXP5080
CMOS 4-bit Single Chip Microcomputer evaluator type For the availability of this product, please contact the sales office.
Description CXP5080 is a CMOS 4-bit single chip microcomputer of piggyback/evaluator combined type which has been developed for functional evaluation of the CXP5084/5086. Features * Instruction cycle * * * * * 64 pin PSDIP (Ceramic) 64 pin PQFP (Ceramic)
Piggyback/
* * * * * * * *
3.8s/4.19MHz (CXP5080) 1.9s/4.19MHz (CXP5080H) ROM capacity Maximum 8K bytes (EPROM 27C64, LCC/DIP type 27C64) RAM capacity 400 x 4 bits (Including stack, display area) 32 general purpose I/O ports 16 large current output ports LCD controller/driver (Enables to direct drive) -- Enables to specify the segment output of 24, 20 and 16 optionally -- Enables to select program of the duty, 1/2, 1/3 and 1/4 -- 1/3 bias 2 external interruption input pins 8-bit timer, 8-bit timer/event counter and 18-bit time base timer, independently controlled Arithmetic and logical operations possible between the entire RAM area, l/O area and the accumulator by means of memory mapped I/O Reference to the entire ROM area is possible with the table look-up instruction 2 kinds of power down modes of sleep and stop Power on reset circuit (mask option) The oscillation circuit may be optionally specified as the crystal oscillation type or the CR oscillation type 64-pin ceramic SDIP/QFP
Note) Mask options are determined according to the CXP5080 category. For details refer to the product list. Structure Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E61113A7Z-PS
CXP5080
Block Diagram
(Enables to specify the I/O with bit unit)
(Enables to specify the I/O with port unit) 4 4 Port D
(Combined use of mask with segment output, optional.) 4 Port E 4 Port F
Port A
Port B
Port C
Register
ALU Accumulator
Program counter (13)
Data memory 400 x 4 bits Stack
Flag Address buffer 13 Timer (8) Timer/counter (8) Serial I/O (8) A0 to A12 I0 to I7 8 Instruction input buffer
Data memory
Interruption control
Instruction control
VL VLC1 VLC2 VLC3 8
LCD controller/driver
Time base timer (18)
EXTAL Port X 16 4 WP PX3/SI PX1/SOB PX0/SC PX3/EC PY2/INT2 INT1 PX2/SOA RST PY1 PY0 VDD VSS Port Y Clock control XTAL
SEG16 SEG0 COM0 to to to SEG23 SEG15 COM3
(Combined use of serial I/O)
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CXP5080
Pin Assignment 1 (Top View) 64 pin PSDIP Package
VL XTAL EXTAL RST WP INT1 PY0 PY1 PY2/INT2 PY3/EC PX0/SC PX1/SOB PX2/SOA PX3/SI PD0 PD1 PD2 PD3 PC0 PC1 PC2 PC3 PB0 PB1 PB2 PB3 PA0 PA1 PA2 PA3 PESEL VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 VDD A12 A7 A6 A5 A4 A3 A2 A1 VDD 28 VDD 27 VDD 26 A8 25 A9 24 A11 23 VSS 22 A10 21 VSS 20 I7 19 I6 18 I5 17 I4 16 I3 15
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VDD VLC3 VLC2 VLC1 COM0 COM1 COM2 COM3 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16/PF0 SEG17/PF1 SEG18/PF2 SEG19/PF3 SEG20/PE0 SEG21/PE1 SEG22/PE2 SEG23/PE3
10 A0 11 I0 12 I1 13 I2 14 VSS
Note)
PESEL pin serves to switch the I/O signal of the socket on top of the package from interface with the evaluator (Eva mode) to interface with EPROM (Piggyback mode). Setting PESEL pin to H Ievel brings Eva mode to enable the connection with the evaluator. Setting it to L level brings piggyback mode to enable the mounting of EPROM. For QFP piggyback, it is necessary only to exchange EVACAP (or EPROM) for EPROM (or EVACAP) and no other special measures are required.
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CXP5080
Pin Assignment 2 (Top View) 64 pin PQFP Package
EXTAL
COM0
COM1
64 63 62 61 60 59 58 57 56 55 54 53 52 PY0 PY1 PY2/INT2 PY3/EC PX0/SC PX1/SOB PX2/SOA PX3/SI PD0 PD1 PD2 PD3 PC0 PC1 PC2 PC3 PB0 PB1 PB2 1 PESEL PESEL 2 A12 VDD 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A6 5 A5 6 A4 7 A3 8 A2 9 A1 10 A0 11 NC 12 I0 13 14 15 16 17 18 19 20 VSS NC I1 I2 I3 I4 I5 A7 4 51 50 49 48 47 29 A8 28 A9 27 A11 26 NC 25 VSS 24 A10 23 VSS 22 I7 21 I6 46 45 44 43 42 41 40 39 38 37 36 35 34 33 COM3 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16/PF0 SEG17/PF1
VDD
3
2
1 32 31 30
PB3
PA0
PA1
PA2
PA3
VSS
NC
SEG23/PE3
SEG22/PE2
VDD
SEG21/PE1
SEG20/PE0
SEG19/PF3
Note 1) PESEL pin serves to switch the I/O signal of the socket on top of the package from interface with the evaluator (Eva mode) to interface with EPROM (Piggyback mode). Setting PESEL pin to H Ievel brings Eva mode to enable the connection with the evaluator. Setting it to L level brings piggyback mode to enable the mounting of EPROM. For QFP piggyback, it is necessary only to exchange EVACAP (or EPROM) for EPROM (or EVACAP) and no other special measures are required. Note 2) Do not make any connections to NC pin.
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SEG18/PF2
COM2
XTAL
INT1
VLC3
VLC2
VLC1
RST
VDD
WP
VL
CXP5080
EPROM read timing (Ta = -20 to +75C, VDD = 4.5 to 5.5V, VSS = 0V reference) Item Address Data input delay time Address input holding time Symbol Pin A0 to A12 I0 to I7 A0 to A12 I0 to I7 0 Min. Max. 300 Unit ns ns
tACC tIH
0.8VDD A0 to A12 Address data 0.2VDD
tACC
tIH
0.8VDD I0 to I7 Input data 0.2VDD
Products List Optional item Package ROM capacity Speed Oscillation type Segment output Output type PY0 and PY1 output type Mask ROM CXP5086 64-pin plastic SDIP/QFP 6K byte Standard/High speed Crystal/CR 16/20/24 Tri-state/ Pull-up resistance/ Open drain Pull-up resistance/ Inverter CXP5080HU02AS CXP5080HU03AS CXP5080HU04AS CXP5080HU02AQ CXP5080HU03AQ CXP5080HU04AQ 64-pin ceramic PSDIP/PQFP EPROM 8K byte High speed Crystal 20 Tri-state 64-pin ceramic PSDIP/PQFP EPROM 8K byte High speed Crystal 24 Tri-state 64-pin ceramic PSDIP/PQFP EPROM 8K byte High speed Crystal 16 Tri-state
Pull-up resistance Hi-Z Existent Existent Input Normal
Pull-up resistance Hi-Z Existent Existent Input Normal
Pull-up resistance Hi-Z Existent Existent Input Normal
Output state during Holding state/Hi-Z standby Pull-up resistance of reset pin Existent/non-existent
Incorporated power Existent/non-existent on reset circuit SOA pin output SOB pin output Normal/Input Normal/Input
Note) All of the above products are combined chips of piggyback and evaluator. -5-
CXP5080
Package Outline
Unit: mm
64PIN PSDIP (CERAMIC) 750mil
+ 0.74 57.0 - 0.53 0 to 9 64 33
18.76 0.29
1 2.54 0.25
32
1.27 0.25
0.48 0.1 0.9 0.2
1.778 0.2
SONY NAME EIAJ NAME JEDEC CODE
3.4 0.3
10.16 MAX
PSDIP-64C-021 ADIP064-C-0750-AF
64PIN PQFP (CERAMIC)
PIN No.1 INDEX INDEX 18.7 16.3 0.2 PIN No.1 INDEX
64
52
52
0.25 0.05
19.05 0.3
15.24
64
1
51 51
1
4.5 1.27 01.3
22.3 0.3
18.12 0.2
24.7
12.02
14.22
6.0
0.3
20 9.48 11.66 15.58 0.2
32
1.3 0.3 1.5
19
33
1.0
33
19
32 0.7
20
SONY NAME EIAJ NAME 9.32 MAX JEDEC CODE
PQFP-64C-L01 AQFP054-C-0000-A
3.07 0.3
+ 0.05 0.15 - 0.02
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0.4 0.08
1.0 0.05

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